`timescale 10ns / 1ps
`include "PicoDefines.v"
module rhdl_ClockGen(CLOCKIN,CLOCK_ENABLE, ClockOut);

input CLOCKIN;  
input CLOCK_ENABLE;                                                      //Raw Clock Input from Physical Pin
output ClockOut;                                                      //200 MHz Clock Output to Peripherals

wire ClockOutPreBuf;                                                  //Unbuffered DCM Output
wire Reset;                                                           //Reset Signal (Hold high for 4 cycles (80nS)
wire Feedback, FeedbackBuffered;                                      //Feedback for the DCM

`ifdef ENABLE_DEBUG_TAPS
wire DCMLocked;                                                       //DCM Locked Signal (For use in Chipscope)
//synthesis attribute KEEP of DCMLocked is TRUE;
`endif 

//-----------------------------Reset Circuit------------------------------//
SRL16 RESET_SRL(.Q(Reset), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLOCKIN), .D(1'b0));
//synthesis attribute INIT of RESET_SRL is 16'hFFFF;
//synthesis translate_off
defparam RESET_SRL.INIT = 16'hFFFF;
//synthesis translate_on

//-----------------------------Clock Buffers------------------------------//
BUFG ClockOutBuf(.I(ClockOutPreBuf), .O(ClockOut));                   //Clock Output Buffer
BUFG FeebackBuf (.I(Feedback), .O(FeedbackBuffered));                 //Feedback Buffer

//-----------------------------DCM Primitive------------------------------//
DCM_ADV CLOCK_DCM(.CLKFB(FeedbackBuffered),                           //Phase control feedback
                  .CLKIN(CLOCKIN),                                    //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(Reset),                                        //Reset Signal
                  .CLKDV(),
                  .CLKFX(ClockOutPreBuf),
                  .CLKFX180(),
                  .CLK0(Feedback),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
`ifdef ENABLE_DEBUG_TAPS															 //The locked signal is usefull for debugging with ChipScope
						.LOCKED(DCMLocked),
`else
                  .LOCKED(),
`endif
						.PSDONE());


//-----------------Clock speed is set here-------------------//

//synthesis attribute CLKFX_DIVIDE of CLOCK_DCM is "1";
//synthesis attribute CLKFX_MULTIPLY of CLOCK_DCM is "4";
//synthesis translate_off
defparam CLOCK_DCM.CLKFX_DIVIDE = "1";
defparam CLOCK_DCM.CLKFX_MULTIPLY = "1";
//synthesis translate_on

//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM is "1X";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM is "MAX_SPEED";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM is "TRUE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM is "TRUE";
//synthesis attribute FACTORY_JF of CLOCK_DCM is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM.CLK_FEEDBACK = "1X";
defparam CLOCK_DCM.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM.CLKIN_PERIOD = "20";
defparam CLOCK_DCM.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM.DCM_PERFORMANCE_MODE = "MAX_SPEED";
defparam CLOCK_DCM.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
defparam CLOCK_DCM.PHASE_SHIFT = "0";
defparam CLOCK_DCM.STARTUP_WAIT = "TRUE";
defparam CLOCK_DCM.FACTORY_JF = "F0F0";		 
//synthesis translate_on

endmodule
